There were 2 rounds of technical interview. Basic system verilog and UVM based questions were asked. Almost all the concepts they touched. additional to that questions related to the projects from the resume.

The interview process was moderate in difficulty. They asked questions from SystemVerilog, UVM, and also included some coding-related questions. Their process was well-structured, intact, and carried out in a professional manner. The panel was friendly and gave sufficient time to think before answering. Overall, it was a balanced interview experience that tested both theoretical knowledge and practical problem-solving skills.