J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 jour. J'ai passé un entretien chez Intel Corporation en mai 2012
Entretien
On-site interview.
During seven hours, I met several interviewers who have various backgrounds. I got questions about my major, electronics, almost all. Honestly, it was difficult to answer those questions because I just prepared my current research area (I'm a Ph.D. candidate) and I forgot electronics.
Although I could not get an offer, I think that this interview is a good experience to me. I could understand what interviewers asks and how I should answer now.
If you would be a student of an electrical and computer engineering, I recommend that you should review a book of electronics, especially a CMOS circuit.
Questions d'entretien [1]
Question 1
A simple circuit (four CMOS). If one CMOS is not working, what happens on an output?
J'ai passé un entretien chez Intel Corporation (Guadalajara, Jalisco)
Entretien
Largo, cansado, solo si tienes conexiones en Intel te llaman, el proceso es largo, las preguntas técnicas son fáciles, sin embargo si eres de otro estado tus posibilidades de ser contratado bajan
The interview started with a short introduction about myself. The interviewer then explained the role and the responsibilities. They asked me to describe my final project in detail and followed with a few technical questions.
Questions d'entretien [1]
Question 1
Can you walk me through your final project and explain the main technical challenges you handled?
In very much details. Block diagram and code.
J'ai passé un entretien chez Intel Corporation (Heredia)
Entretien
Apply through the web site, answer some questions about experience and knowledge of Verita in tools.
After that you get an email asking for some more information (availability and such). Next it’s a short phone call to verify your English level.
After that there’s a technical interview and then a final interview
Questions d'entretien [1]
Question 1
Had to create a flip-flop with asynchronous and other with synchronous reset using system verilog