J'ai postulé via un recruteur. Le processus a pris 1 jour. J'ai passé un entretien chez Intel Corporation (Portland, OR) en déc. 2011
Entretien
The interviewer/manager called me the day before to ask if I was interested in interviewing for a HW design position. This position was an entry-level/college grad position with Intel UMG to get Intel chips into phones. Questions were mostly about hardware not overly difficult but you definitely need to know your IA and embedded systems basics. I personally got very nervous to the point that I couldn't remember some of the most rudimentary things. The guy understood that I was nervous and was very nice and gave me feedback on what he thought of my answers.
Questions d'entretien [2]
Question 1
when you open your computer, what are the parts that you see. Describe their functionality and how they all work together.
J'ai passé un entretien chez Intel Corporation (Guadalajara, Jalisco)
Entretien
Largo, cansado, solo si tienes conexiones en Intel te llaman, el proceso es largo, las preguntas técnicas son fáciles, sin embargo si eres de otro estado tus posibilidades de ser contratado bajan
The interview started with a short introduction about myself. The interviewer then explained the role and the responsibilities. They asked me to describe my final project in detail and followed with a few technical questions.
Questions d'entretien [1]
Question 1
Can you walk me through your final project and explain the main technical challenges you handled?
In very much details. Block diagram and code.
J'ai passé un entretien chez Intel Corporation (Heredia)
Entretien
Apply through the web site, answer some questions about experience and knowledge of Verita in tools.
After that you get an email asking for some more information (availability and such). Next it’s a short phone call to verify your English level.
After that there’s a technical interview and then a final interview
Questions d'entretien [1]
Question 1
Had to create a flip-flop with asynchronous and other with synchronous reset using system verilog