J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 3 semaines. J'ai passé un entretien chez Qualcomm (Toronto, ON) en févr. 2019
Entretien
I applied through university career fair, there they asked me to explain one of the projects I had done and how I rate my verilog. Then after 3 weeks they emailed me to set phone interview. On the phone interview they explained what roles are they looking for and a little about my background and then series of technical questions about clock domain crossing, setup and hold time, clock skew
Questions d'entretien [1]
Question 1
In ASIC design is hold time more critical of setup time?
J'ai passé un entretien chez Qualcomm (Mississauga, ON)
Entretien
I had 6 rounds total. The first two were with senior directors who really drilled into my past projects and took time to walk me through the team's work and org structure — they seemed genuinely engaged.
Then I had three rounds with staff engineers. We covered some coding questions I wrote edge detection logic and an FSM, but I made a couple of mistakes on the first pass that I caught and corrected when the interviewers pointed them out. We also talked about DV concepts like reference models and how to build self-checking testbenches.
The final round was with a senior MTS from the Markham office, and it was pure behavioral no technical questions, just asking about my background and team fit.
J'ai passé un entretien chez Qualcomm (Toronto, ON)
Entretien
2 stage interview with first interview to get to know the position and team. 2nd interview was ~1hr long with all technical questions. Write a counter, make a nand gate with muxes, name some cdc/lint violations.
Questions d'entretien [1]
Question 1
Write verilog for a counter, make a nand gate with muxes
Had a phone interview first. Then was called for on site interview. Had 6 interviews. One of them was on software, One was on basic circuits (undergrad level), other were SRAM design.