J'ai postulé en personne. Le processus a pris 4 semaines. J'ai passé un entretien chez Synopsys (Bengaluru) en déc. 2018
Entretien
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
Questions d'entretien [1]
Question 1
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
J'ai passé un entretien chez Synopsys (Canonsburg, PA)
Entretien
There were several stages to the interview process. Required a lot of time, but in the end, it was well worth the effort. The interview panel was very supportive and encouraging.
The interview process was seamless, featuring a moderate level of questions. The supportive demeanor of the interviewer enhanced the overall experience, making it smooth and conducive to a positive interaction.
Questions d'entretien [1]
Question 1
It covered concepts of Digital Circuits, VLSI Design. Combinational vs Sequential circuits, FFs, FSM.
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Synopsys (Bengaluru) en sept. 2022
Entretien
The Interview was of 3 rounds.
1. Basic Introduction and 1 technical question by the Manager.
2. Technical round by a technical lead.
3. Technical round by another technical lead.
Questions d'entretien [1]
Question 1
If there are setup and hold violations and you are at the last stage what would you choose to fix either setup? or hold? and why?