J'ai postulé via une autre source. J'ai passé un entretien chez SmartDV Technologies (Chittoor)
Entretien
There is one aptitude round consist of digital electronics and basic aptitude and basic questions of C programming and 3 rounds
of technical phone interview are there consists of Verilog related questions
Questions d'entretien [1]
Question 1
Explain about basic questions of digital electronics
J'ai postulé en ligne. Le processus a pris 3 jours. J'ai passé un entretien chez SmartDV Technologies (Bengaluru) en sept. 2025
Entretien
The interview process typically has three stages:
Written / Online Test – Covers digital electronics, Verilog/SystemVerilog basics, C programming, and some aptitude/number system problems.
Technical Interviews (1–2 rounds) – Focus on digital design fundamentals (flip-flops, FSMs, counters), Verilog/SystemVerilog coding tasks, and UVM methodology basics (driver, monitor, scoreboard, coverage). Candidates may also be asked about their academic projects.
HR / Managerial Round – General discussion about background, interest in verification, work culture fit, and salary/relocation details.
Questions d'entretien [1]
Question 1
How I Answered:
I explained that blocking assignments (=) execute sequentially, one after the other, like normal C statements, and they can cause race conditions if used in clocked always blocks.
Non-blocking assignments (<=) allow all right-hand side values to be evaluated first and then update the left-hand side at the end of the time step, making them ideal for modeling synchronous logic like flip-flops.
J'ai passé un entretien chez SmartDV Technologies (Bangalore Rural)
Entretien
It happened one full day. I underwent three rounds.Two virtual technical and one direct technical .only basics questions in digital electronics,vlsi,oops were asked in all the three rounds . May be they will conduct one general hr round
Questions d'entretien [1]
Question 1
asked to draw half adder .number conversions were asked
J'ai postulé en personne. J'ai passé un entretien chez SmartDV Technologies (Chennai) en sept. 2024
Entretien
Good interview with the good panel members .it was an average question everything related to the system Verilog UVM perl verific language and their syntax how to use those variables