The interview is mostly centered floorpan analysis and congestion removal.The major topic is STA and STA fix methods.Another topic of interest would be low power design.They will ask you lot of questions especially in terms of setup and hold fixing scenarios.

The interview process is very smooth. The questions will focus on core concepts like CMOS, digital logic, and the overall VLSI flow. They'll also ask about more specific topics such as timing, IC reliability, IR-drop analysis, and power integrity. Be ready to show your understanding of these key areas.