RISC(Reduced Instruction Set Computing) - is a CPU design strategy based on the insight that "simplified instruction set" provides higher performance with a microprocessor architecture(micro-architecture) capable of executing them using fewer cycles per instruction(CPI). This is opposed to Complex Instruction Set (CISC) computing. A general RISC system uses small, highly optimized set of instructions rather than a more versatile set of instructions.Another common trait is that RISC systems use the load/store architecture, where memory is normally accessed only through specific instructions, rather than accessed as part of other instructions like add. Well-known RISC families include MIPS(ISA),RISC(Berkeley's RISC implementation) in SPARC, Power (including PowerPC), DEC Alpha, AMD 29k, ARM, Intel i860 and i960. (Edited) Source - Wiki