Got the interview when they are on campus visit. asked several computer hardware design questions such as how to change a clock signal to half the frequency and 50% duty cycle and a few C questions such as what is a friend class. what the key word volatile keyword means in C. overall easy interview.

Interview was good, Interviewers were friendly, overall experience was good, mostly focused on SRAM and System Verilog. In first round they only concentrated on SRAM design project and second round was with a team lead as they work mostly with system verilog, they asked me to implement a problem in system verilog.