J'ai postulé via une agence de recrutement. Le processus a pris 3 semaines. J'ai passé un entretien chez Cirrus Logic (Austin, TX) en juill. 2017
Entretien
This is not a place that experienced/senior engineers should look to. They seem to have more work than people to do it and are looking to scale through hiring more bodies than changing how they actually do verification reuse. They rely mostly on external recruiters not only for finding candidates but also as agents throughout the whole process so you're mostly dealing with a distant third party headhunter who knows little about the role, industry, or expectations.
The pre-interview process involved a prescreen call and testbench coding exercise that a candidate does on their own time followed by a technical review call. The onsite interview was not effectively geared towards a Senior person and also involved an on-demand coding activity which was vague and wouldn't reveal much about DV expertise.
Despite initial positive feedback and follow-up calls, the company took over 2 weeks to respond (via their 3rd party head hunter) with disappointing news and absolutely no other feedback.
Questions d'entretien [1]
Question 1
Write a constraint expression for an 8-bit value with the same number of 1/0 bits
J'ai postulé en ligne. J'ai passé un entretien chez Cirrus Logic (Austin, TX) en août 2019
Entretien
2 Phone screens followed by onsite. I found their interview process to be apt and extracts the best out of the candidate. 1 phone screen is more of behavioral and another one is take home project follwed on explanation and other DSP questions
J'ai postulé en ligne. Le processus a pris 2 semaines. J'ai passé un entretien chez Cirrus Logic (Raleigh, NC) en févr. 2019
Entretien
One 45 minutes phone interview which is mostly the basics of the digital design concepts and OOP concepts followed by one and half hour of on-campus interview. It was a panel interview round.
Questions d'entretien [1]
Question 1
Questions related to projects mentioned on the resume, Constraint questions, Write the verilog code and testbench for the given system