J'ai passé un entretien chez Cadence Design Systems (Ahmedabad)
Entretien
Interview process consists of 3-4 rounds. First round is a MCQ test consisting of digital electronics, Verilog, aptitude and C programming. Then 2 technical rounds and 1 HR round. The interview mainly focused on Verilog, systemVerilog, C programming, digital electronics, memory design, UVM, oops concepts, etc.
Questions d'entretien [1]
Question 1
Synchronous FIFO (based on the project), Memory design, C programming questions
J'ai postulé en ligne. Le processus a pris 3 jours. J'ai passé un entretien chez Cadence Design Systems (Bengaluru) en avr. 2021
Entretien
Totally it was a nice experience, the interview went around a lot of Design and Verification concepts like Verilog, System Verilog (SV), and Universal Verification Methodology (UVM).
Also asked about the projects that I have done before and what were the pain points that had been solved & my role in it.
Questions d'entretien [1]
Question 1
Explain different phases in the UVM and their importance?