J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Cadence Design Systems (Noida) en sept. 2024
Entretien
race condition is a bug that occurs when the outcome of a system depends on the unpredictable timing or sequence of events. It happens when multiple concurrent threads (or a thread and an ISR) access a shared resource (like a global variable) without proper protection, and at least one of those accesses is a write. The classic example is a "read-modify-write" operation.
Questions d'entretien [1]
Question 1
on resume projects and other basic questions on digital technology
J'ai postulé en ligne. Le processus a pris 1 semaine. J'ai passé un entretien chez Cadence Design Systems (Cork) en mars 2026
Entretien
This was a interview for a intern position for a digital logic design role
1. HR call to setup interview
2. Technical Round with Hiring Manager
3. Behavioral Round with another Manager
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Cadence Design Systems (Pune) en févr. 2026
Entretien
1 screening,2 tech and 1 HR. Technical easy-medium. Focus on core programming and puzzle type questions.
Only move on to the tech interview if 5min screening goes well so make sure your resume stands out.
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 semaine. J'ai passé un entretien chez Cadence Design Systems (Pune) en févr. 2026
Entretien
I was interviewed for two teams. One was focused heavily on Java and OOP in Java, and they asked to design systems using OOP concepts. The other team asked questions on all CS fundamentals such as OOP, CN, OS, and medium-level DSA questions as well, with focus on C, C++, and Python (not Java).
Questions d'entretien [1]
Question 1
1. Medium-level DSA questions
2. Designing systems using OOP concepts