J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Apple (Cupertino, CA) en oct. 2024
Entretien
This was an initial screening for design verification intern. He asked Alot of hard questions specifically about system Verilog for verification and protocols. The questions were very niche aswell. I found myself struggling to answer alot of the questions because it was material i haven't really learned yet.
Questions d'entretien [1]
Question 1
How does I2C manage situations where a device needs more time to process data before the next clock pulse?
J'ai passé un entretien chez Apple (San Diego, CA)
Entretien
There were 1 screening and 6 panel rounds and it was difficult especially UVM part also they AMBA protocols basic design questions like fsm fifo and all and more focus on constraints
Questions d'entretien [1]
Question 1
UVM based questions and Assertions and constraints
J'ai postulé en ligne. J'ai passé un entretien chez Apple (Sunnyvale, CA) en mars 2026
Entretien
I had a screening round that started directly without any introduction. I was asked questions about my resume, mainly about my projects. After that, I was given a coding question.
first asking about the tool experience, asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake , how do you deal with CDC problems, how to do the STA analysis, then final having a coding question
Questions d'entretien [1]
Question 1
implementation of driver class based on the figure they gave