J'ai postulé en ligne. J'ai passé un entretien chez Apple en févr. 2026
Entretien moyen
Candidature
J'ai postulé en ligne. Le processus a pris 2 mois. J'ai passé un entretien chez Apple en avr. 2021
Entretien
First talking to the recruiter and he found out I was interviewing other groups. Immediately setting up an interview with the hiring manager. She asked a mixture of technical and resume questions. Questions on CDC and digital design and also wireless communications. Next, I was invited for first round of virtual onsite interview. Two team members and again the hiring manager. Team members asked average questions and I was comfortable but the hiring manager started attacking me and asked both coding and technical questions. I did not get the second onsite interview.
Questions d'entretien [1]
Question 1
How to implement square root in hardware?
Bunch of matlab codes to go over and figure out how to implement a piece of algorithm.
Many verilog questions and designs.
CORDIC algorithm (as I had experience on that)
1 - Applied to a different team but wasn't a good fit (was referred to another team). 2 - Got scheduled an interview with the hiring manager. A successful interview would lead to 6 more interviews with engineers. 3 - Didn't make it past the technical screen for my level.
Questions d'entretien [1]
Question 1
FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
The interview process for VLSI digital design typically includes an initial screening, technical interviews covering digital design concepts, RTL coding, timing analysis, logic synthesis, verification, problem-solving, and sometimes a practical coding task.
J'ai postulé en ligne. J'ai passé un entretien chez Apple
Entretien
applied online, got call after a long time, 1 round video call interview, talking about hardware design flow, low power. Asked a question someone already posted here long time ago, surprised.