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      Entretien pour CPU Design Verification Engineer

      23 févr. 2020
      Candidat à l'entretien anonyme
      Portland, OR
      Aucune offre
      Expérience négative
      Entretien moyen

      Candidature

      J'ai postulé en ligne. Le processus a pris 4 jours. J'ai passé un entretien chez Ampere Computing (Portland, OR) en févr. 2020

      Entretien

      There were 2 phone interviews, first to screen and second for technical. The first interviewer told me the second would call me. Instead, they e-mailed me 1 minute before the interview inviting me to join a Zoom meeting. I had never used Zoom before, but it was fairly quick to setup. I don't understand why 2 people at Ampere (first and second interviewers) can't talk to each other -- why tell a candidate you're going to call THEM but then at the last minute prior do something different? You're telling me that they didn't have the time to inform the interviewee, "Hey I'm not going to call you but instead we will use Zoom and I will send you a link"? There were a few days between interviews, so they certainly had this time available. At first the interview seemed alright but eventually I could see this place would be miserable to work at. The second interviewer didn't care about problem solving ability yet that's what they claimed to be seeking out. They also laughed multiple times at my responses, which felt out of place if not rude and unprofessional. At one point during the coding example they asked if the problem could be solved a different way. Could a programming example be solved more than one way? Are you kidding me? Of course it can. What a waste of my time. Trying to demonstrate to this person my thinking ability was shortchanged by their ego to dominate the conversation with how much they don't think I understood the concepts related to pre-reqs for the job. It also surprises me the job posting stated a myriad of skills, Verilog, System Verilog, Computer Architecture, Unix Shell, Python, and so on, yet they truly only asked Computer Architecture questions. Had I know that's all they were going to ask then I wouldn't have bothered reviewing Verilog. Seems to be a disconnect between what the hiring manager wants in a candidate versus the job description that gets posted. The first interviewer also told me any skills could be learnt on the job. Yet the second interviewer seemed prepared to doom me from the start regardless of potential.

      Questions d'entretien [6]

      Question 1

      What is a hardstuck bug you have encountered during a project?
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      Question 2

      How does branch prediction work? What hardware mechanisms alleviate mis-predicts?
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      Question 3

      Give examples of how loops work in ARM?
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      Question 4

      Tell me about your background?
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      Question 5

      How many blocks are in an N way set associate cache?
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      Question 6

      Describe virtual memory and the Memory Management Unit?
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      8