J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 3 semaines. J'ai passé un entretien chez Ambarella
Entretien
On campus career fair submitted resume, phone interview. Totally technical, questions on clock skew/jitter, string detector, verilog data width and implementing gate with MUX
Questions d'entretien [1]
Question 1
Compare the advantage of shift register and FSM in implementing string detector
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 4 semaines. J'ai passé un entretien chez Ambarella (Santa Clara, CA) en févr. 2013
Entretien
Submitted resume at the career fair, and then get e-mails to have phone interview. Three rounds of phone interviews.
Questions d'entretien [1]
Question 1
1. Basic circuit design and logic design question
2. Basic verilog question (e.g. verilog module to swap 2 variables, 4-to-1 mux etc.)
3. Write a verilog testbench module which generates 2 output signals:
1) clock - at 1GHZ
2) reset - asserted (1) for first 100 cycles and then deasserted (0)
4. 8 entry FIFO module
5. What are the 2 components of a chip power and how will you reduce each one?