Questions d'entretiens - Ic engineer

284

Questions d'entretien pour Ic Engineer partagées par les candidats

Principales questions d'entretien

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Qualcomm
On a demandé à Analog & Mixed-Signal IC Design Engineer...26 juin 2012

How to make sure the 2-stage opamp is stable? How does the compensation work?

5 réponses

Using Miller compensation. A compensation capacitor across the 2nd stage to create pole splitting. A series resistor to the cap might be needed to solve the rhp zero problem Moins

Using compensation capacitor, which makes the low frequency pole's frequency become lower and high frequency pole's frequency higher, so OPmap is more stable. Moins

Using compensation network including capacitor and resistor and monitoring the phase margin and gain margin as well. Moins

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Analog Bits

1) Given an NMOS, 5V on Drain, 4V on Gate, what is voltage on source? 2) What happens when using a NMOS to pull up and/or a PMOS to pull down? 3) Given a rotating disk that's 1/4 black and 3/4 white, assume you have two sensors 90 degrees apart. How can you determine the direction the disk is rotating (clockwise vs counterclockwise) with some cmos circuit?

3 réponses

a simple phase error detector (lead /lag) would work (frequency not needed), e.g. cw gives phase error 90 degrees, ccw gives 270 degrees, with b/w sensors analogous to rise and fall of a clock edges. Moins

2) what if you have a leakage

2) You get a Vt drop on the output.

Broadcom

Just some C++basics since I had not prepared C++ at all. Arrays and pass by reference and value.

2 réponses

overall was good interview experience

There's a lot of elements to typically cover in these questions, clarifications, scoping, making sure you're answering the actual question the interviewer is looking for you to answer, etc. Could be worth doing a mock interview with one of the Prepfully Broadcom IC Design Engineer experts... they've worked in the role so they clearly know how to get through the interview. prepfully.com/practice-interviews Moins

Marvell Technology

amplifier sizing

2 réponses

key is to recognize the most import mosfets based on various topologies.

It's weird that digital IC design also asked analog question. Or my understanding is wrong If High gain is required, choose larger length, otherwise minimum length for max fT. Moins

Freescale Semiconductor

Willing to move/commute?

1 réponses

Yes

Broadcom

how to bias a cascode current mirror? how you would layout it?

2 réponses

- Biasing the gate of the cascode devices with a ratio of 1/5 or 1/6 (W/L) to ensure the lower device stay in saturation. If we have a ratio lower than 1/6, then we are decreasing the minimum Vo for the cascode device. - The 1/5 (W/L) device while having a long channel, its better to layout it with 5 (W/L) transistors connected in series. Why? to decrease the variation of Vt of long channel transistors Moins

Mirroring transistors has to be matched and interdigitized to reduce 2nd order effects. Using multiplier matches the transistor better. Moins

International Rectifier

What do you know about the HEXFET geometry (the layout of the devices), and why would this particular geometry be an advantage for the applications in which HEXFETs are normally used?

1 réponses

The general answer is that the geometry provides MUCH better (lower) channel On resistance, and much greater immunity to punch-through. I had, fortunately, read enough about the subject to be able to discuss it intelligently. My responses didn't cover all details, but it was enough to allow meaningful discussion (and I learned a few things as well!) Moins

Vicor Corp.

Draw and SAR ADC block diagram

1 réponses

The block diagram needs a clock, comparator, register, DAC, sample and hold

Vicor Corp.

how would you supress latch up in the NP N P structure?

1 réponses

The Npn base and PNP have resistive connection to the supply rails. if the resistance is small enough, the latch will never reach positive feedback. Moins

Vicor Corp.

draw a bandgap circuit and explain it

1 réponses

write the equations for Ic vs Vbe, solve for d Vbe = KT ln Area ratio

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