Question d'entretien d'embauche NVIDIA: Draw a two-put NAND gate and ... | Glassdoor.ca

Question d'entretien d'embauche

Entretien de Physical Design Engineer Santa Clara, CA (États-Unis)

Draw a two-put NAND gate and size it, assuming the ratio of

  PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?
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Réponse de l'entretien

4 réponses

4

input pattern affect delays, parasitic capacitance effect

Candidat à l'entretien, le 17 mars 2011
4

Case 1: Lets say A is a stable '1' , the intermediate node between the A & B transistor will be charged to VDD-Vt. When B changes from '0' to '1', it takes time for that node to discharge.
Case 2: Lets say B is a stable '1', the intermediate node is already discharged. When A changes from '0' to '1',the output will switch faster since the intermediate node is already discharged.

Utilisateur anonyme, le 5 mars 2015
0

for the second scenerio, there will be high leakage current compared to the first scenario, as A will be off for more time while having Vds = Vdd which makes leakage high, it is not the same situation for the first scenario.

H B, le 23 août 2019
0

This question is actually not as easy as it sounds. The key in questions like this, is to be ready for all the inevitable follow-up questions and back-and-forth that typically happens, as the interviewer really tries to understand how you think.

Maybe do a mock interview with one of the Nvidia Physical Design Engineer experts on PrepTick to get a real-world answer? They give lots of guidance and pro tips on how to deal with this kind of stuff...

https://www.preptick.com/practice-interviews-swe

Utilisateur anonyme, le 17 janv. 2020

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